V.R. Devanathan

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test

V.R. Devanathan, C.P. Ravikumar, V. Kamakoti · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 2007 · 38 citations

Engineering, Power Optimization (Eda), Scan Compression +25

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test

V.R. Devanathan, C.P. Ravikumar, V. Kamakoti · 2007 · 27 citations

Engineering, Vlsi Design, Process Variation +23

On Power-profiling and Pattern Generation for Power-safe Scan Tests

V.R. Devanathan, C.P. Ravikumar, V. Kamakoti · 2007 · 25 citations

Engineering, Measurement, Power Optimization (Eda) +22

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test

V.R. Devanathan, C.P. Ravikumar, Rajat Mehrotra et al. · 2007 · 24 citations

Engineering, Power Optimization (Eda), Diagnosis +17

Methodology for low power test pattern generation using activity threshold control logic

Srivaths Ravi, V.R. Devanathan, Rubin Parekhji · International Conference on Computer Aided Design · 2007 · 20 citations

Hardware Security, Electrical Engineering, Engineering +15