V.R. Devanathan - Concepedia

Author

V.R. Devanathan

Texas Instruments (United States)

Also Known As

V Devanathan, V R Devanathan, V. R. Devanathan, V.R. Devanathan

Publications

266

Citations

H-Index

Concepts

All Affiliations

Texas Instruments (United States)Indian Institute of Technology Madras Texas Instruments (India)

About

V.R. Devanathan is an author at Texas Instruments (United States) specializing in engineering, hardware security, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	7	7	163
2	Computer Engineering	7	7	163
3	Electrical Engineering	6	6	151
4	Computer Science	4	4	102
5	Systems Engineering	1	1	38

V.R. Devanathan

Publications

163

Citations

H-Index

Page 1

	Year	Citations
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test V.R. Devanathan, C.P. Ravikumar, V. Kamakoti Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium EngineeringPower Optimization (Eda)Scan CompressionDft ArchitectureComputer Architecture	2007	38
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test V.R. Devanathan, C.P. Ravikumar, V. Kamakoti EngineeringVlsi DesignProcess VariationProcess Variation InformationPower Optimization (Eda)	2007	27
On Power-profiling and Pattern Generation for Power-safe Scan Tests V.R. Devanathan, C.P. Ravikumar, V. Kamakoti EngineeringMeasurementPower Optimization (Eda)Localized Switching ActivityComputer Architecture	2007	25
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test V.R. Devanathan, C.P. Ravikumar, Rajat Mehrotra, EngineeringPower Optimization (Eda)DiagnosisComputer ArchitectureLeakage Power	2007	24
Methodology for low power test pattern generation using activity threshold control logic Srivaths Ravi, V.R. Devanathan, Rubin Parekhji International Conference on Computer Aided Design Hardware SecurityElectrical EngineeringEngineeringHardware-in-the-loop SimulationCircuit Design	2007	20
Methodology for low power test pattern generation using activity threshold control logic Srivaths Ravi, V.R. Devanathan, Rubin Parekhji Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design Hardware SecurityElectrical EngineeringEngineeringHardware-in-the-loop SimulationCircuit Design	2007	17
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms V.R. Devanathan, C.P. Ravikumar, V. Kamakoti EngineeringVerificationComputer ArchitectureScan ArchitectureFormal Verification	2007	12

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