Rubin Parekhji

An efficient test data reduction technique through dynamic pattern mixing across multiple fault models

Srinivasulu Alampally, Rakshith Thambehalli Venkatesh, Priyadharshini Shanmugasundaram et al. · 2011 · 48 citations

Engineering, Fault Models, Computer Architecture +19

Concurrent error detection using monitoring machines

Rubin Parekhji, G. Venkatesh, S.D. Sherlekar · IEEE Design & Test of Computers · 1995 · 33 citations

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2012 · 29 citations

Engineering, Vlsi Design, Power Optimization (Eda) +17

Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency

Sandeep Goel, Rubin Parekhji · 2005 · 26 citations

Engineering, Structural Patterns, Computer Architecture +24

A Methodology for Designing Optimal Self-Checking Sequential Circuits

Rubin Parekhji, G. Venkatesh, S.D. Sherlekar · 2005 · 25 citations

Engineering, Verification, Formal Methods +6