M. Nakao

Low overhead test point insertion for scan-based BIST

M. Nakao, Susumu Kobayashi, Kazuhisa Hatayama et al. · 2003 · 57 citations

Electrical Engineering, Physical Design (Electronics), Engineering +14

Enhancing Transition Fault Model for Delay Defect Diagnosis

Wu-Tung Cheng, Brady Benware, Ruifeng Guo et al. · 2008 · 38 citations

Fault Diagnosis, Engineering, Mem Testing +20

Accelerated test points selection method for scan-based BIST

M. Nakao, Kazuhisa Hatayama, Isao Higashi · 2002 · 24 citations

Bist Scheme, Engineering, Plural Test Points +16

Application of high-quality built-in test to industrial designs

Kazumi Hatayama, M. Nakao, Yoshikazu Kiyoshige et al. · 2003 · 14 citations

Engineering, Industrial Engineering, Verification +20

A BIST approach for very deep sub-micron (VDSM) defects

Yasuo Satô, T. Ikeya, M. Nakao et al. · 2002 · 13 citations

Engineering, Mem Testing, Computer Architecture +20