Low overhead test point insertion for scan-based BIST

Abstract

This paper presents a practical test point insertion method for scan-based BIST. To apply test point insertion in actual LSIs, especially high performance LSIs, it is important to reduce the delay penalty and the area overhead of the inserted test points. Here efficient test point selection algorithms, which are suitable for utilizing overhead reduction approaches such as restricted cell replacement, test point flip-flops sharing, are proposed to meet the above requirements. The effectiveness of the algorithms is demonstrated by some experiments.