Yoshio Okayama

Process integration of 3D chip stack with vertical interconnection

Kenji Takahashi, Yuichi Taguchi, M. Tomisaka et al. · 2004 · 84 citations

Engineering, Electrical Engineering, Materials Engineering +17

Development of a 2-inch GaN wafer by using the oxide vapor phase epitaxy method

Junichi Takino, Tomoaki Sumi, Yoshio Okayama et al. · Japanese Journal of Applied Physics · 2019 · 38 citations

Engineering, Materials Engineering, Materials Science +17

Extreme reduction of on-resistance in vertical GaN p–n diodes by low dislocation density and high carrier concentration GaN wafers fabricated using oxide vapor phase epitaxy method

Junichi Takino, Tomoaki Sumi, Yoshio Okayama et al. · Applied Physics Express · 2020 · 27 citations · Full text

Engineering, Electrical Engineering, Materials Science +17

Floral design GaN crystals: low-resistive and low-dislocation-density growth by oxide vapor phase epitaxy

Junichi Takino, Tomoaki Sumi, Yoshio Okayama et al. · Japanese Journal of Applied Physics · 2021 · 14 citations · Full text

Engineering, Materials Engineering, Materials Science +16

Characteristics of Vertical Transistors on a GaN Substrate Fabricated via Na‐Flux Method and Enlargement of the Substrate Surpassing 6 Inches

Masayuki Imanishi, Shigeyoshi Usami, Kosuke Murakami et al. · physica status solidi (RRL) - Rapid Research Letters · 2024 · 13 citations · Full text

Engineering, Electrical Engineering, Materials Science +17