S. Pidin

A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films

S. Pidin, Toshihiko Mori, K. Inoue et al. · 2005 · 105 citations

Materials Science, Nmosfet/pmosfet Channel Regions, Electrical Engineering +14

Short-channel single-gate soi mosfet model

Ken Suzuki, S. Pidin · IEEE Transactions on Electron Devices · 2003 · 74 citations

Device Modeling, Electrical Engineering, Engineering +10

MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node

S. Pidin, Toshihiko Mori, Ryo Nakamura et al. · 2004 · 38 citations

Device Modeling, Electrical Engineering, Optimization Guidelines +13

High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

Kenichi Gotō, Y. Tagawa, Hiromichi Ohta et al. · 2004 · 22 citations

Low-power Electronics, Electrical Engineering, Engineering +13

Low standby power CMOS with HfO/sub 2/ gate oxide for 100-nm generation

S. Pidin, Yasuhiro Morisaki, Y. Sugita et al. · 2003 · 15 citations

Engineering, Vlsi Design, Silicon On Insulator +17