Publication | Closed Access
MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node
38
Citations
0
References
2004
Year
Unknown Venue
Device ModelingElectrical EngineeringOptimization GuidelinesEngineeringNmosfet Strain EngineeringNanoelectronicsStress-induced Leakage CurrentBias Temperature InstabilityApplied Physics65-Nm Technology NodeExtensive Numerical SimulationsSemiconductor Device FabricationPower ElectronicsElectronic PackagingMicroelectronicsSemiconductor Device
NMOSFET strain engineering using highly tensile silicon nitride capping layer was studied by way of extensive numerical simulations and device experiments. At 45nm gate length and 1V supply voltage fabricated NMOSFET delivers 1.00mA/ /spl mu/m drive current for off-state current of 40nA/ /spl mu/m and physical gate oxide thickness of 1.25nm(TEM). These data demonstrate the best up to date NMOSFET current drivability. Next, using extensive process simulations to analyze fabricated devices we developed optimization guidelines for NMOSFET strain engineering enabling us further improvement of device current drivability with reducing the gate length.