T. Ikezawa

Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

Hitoshi Wakabayashi, T. Ezaki, Toshitsugu Sakamoto et al. · IEEE Transactions on Electron Devices · 2006 · 38 citations

Device Modeling, Electrical Engineering, Physical Design (Electronics) +11

Atomistic 3D process/device simulation considering gate line-edge roughness and poly-Si random crystal orientation effects [MOSFETs]

M. Hane, T. Ikezawa, T. Ezaki · 2004 · 37 citations

Engineering, Oblique Halo Implantation, Computer-aided Design +19

Investigation of realistic dopant fluctuation induced device characteristics variation for sub-100 nm CMOS by using atomistic 3D process/device simulator

T. Ezaki, T. Ikezawa, M. Hane · 2003 · 26 citations

Engineering, Vlsi Design, Discrete Dopant Atoms +16

Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate

Hidetatsu Nakamura, Tatsuya Ezaki, Toshiyuki Iwamoto et al. · Japanese Journal of Applied Physics · 2004 · 24 citations

Engineering, Surface Si, Integrated Circuits +16

SRAM critical yield evaluation based on comprehensive physical / statistical modeling, considering anomalous non-Gaussian intrinsic transistor fluctuations

Miharu Miyamura, T. Fukai, T. Ikezawa et al. · 2007 · 16 citations

Device Modeling, Electrical Engineering, Physical Design (Electronics) +10