Kab-Jin Nam - Concepedia

Author

Kab-Jin Nam

Samsung (South Korea)

Also Known As

K.J. Nam, Kab-Jin Nam, Kab-jin Nam

Publications

659

Citations

H-Index

Concepts

All Affiliations

Samsung (South Korea)

About

Kab-Jin Nam is an author at Samsung (South Korea) specializing in electrical engineering, engineering, and applied physics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	8	8	629
2	Electrical Engineering	8	8	629
3	Applied Physics	7	7	599
4	Computer Engineering	2	2	80
5	Physics	1	1	23

Kab-Jin Nam

Publications

644

Citations

H-Index

Page 1

	Year	Citations
Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors Suraj Cheema, Nirmaan Shanker, Li‐Chen Wang, Nature Oxide HeterostructuresElectrical EngineeringEngineeringFerroelectric ApplicationOxide Electronics	2022	320
Hot carrier reliability characterization in consideration of self-heating in FinFET technology Minjung Jin, Changze Liu, Jinju Kim, EngineeringFinfet TechnologySemiconductor DeviceDc Hci StressNanoelectronics	2016	71
Negative differential capacitance in ultrathin ferroelectric hafnia Sanghyun Jo, Hyangsook Lee, Duk‐Hyun Choe, Nature Electronics Electrical EngineeringEngineeringFerroelectric ApplicationNegative Differential CapacitanceApplied Physics	2023	57
True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3<sup>rd</sup> Generation Single Diffusion Break Wonbeen Jeong, Do Hyun Kwon, Kab-Jin Nam, EngineeringVlsi DesignEmerging Memory TechnologyComputer ArchitectureIntegrated Circuits	2018	50
A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies Sung-Gi Hur, Jung-Gil Yang, Sang-Su Kim, EngineeringNanodevicesIntegrated CircuitsNanocomputingSilicon On Insulator	2013	47
Investigation of hot carrier degradation in bulk FinFET Eun‐Ae Chung, Kab-Jin Nam, Toshiro Nakanishi, Device ModelingHot Carrier InjectionElectrical EngineeringBulk FinfetEngineering	2017	31
A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond Dong-il Bae, Geum-Jong Bae, Krishna K. Bhuwalka, Electrical EngineeringLogic ApplicationsEngineeringVlsi DesignSige Device	2016	30
Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB Guangfan Jiao, M. Toledano-Luque, Kab-Jin Nam, EngineeringSige Valance BandIntegrated CircuitsSemiconductor DeviceElectronic Engineering	2016	23
Design Guidelines of Thermally Stable Hafnia Ferroelectrics for the Fabrication of 3D Memory Devices Giuk Kim, Hunbeom Shin, Taehyong Eom, 2022 International Electron Devices Meeting (IEDM)	2022	15

Page 1