A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

Abstract

This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC and AC performances of Si NW MOSFETs on NW diameter (D <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</inf> ) and gate oxide thickness has been investigated. A Si NW device with the scaled D <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</inf> of 9nm and thin equivalent oxide thickness (EOT) of 0.9nm improved both on-current and electrostatic characteristics. Finally, a Nanowire-On-Insulator (NOI) structure has been proposed to enhance the AC performance of a multiple-stacked NWs structure, which improves DC performance but has the issue of high parasitic capacitance. As a result, the simulated AC performance of a triple-NOI structure was improved by around 20% compared to conventional triple NW structure.