2018 · 51 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignDevice ScalingMicrofabrication ProcessesPhysical DesignVery-large-scale Integration LayoutCmos ScalingComplementary Metal-oxide-semiconductor ScalingFin Field-effect Transistor ScalingGate-all-around Transistor ScalingPlanarizationTechnology ScalingTransistor Sizing
7nm platform technology that takes full advantage of EUV lithography was developed, where EUV was straightforwardly used for single patterning of MOL and BEOL, not just as a means for cutting of SADP/SAQP. The combination of 27nm fin pitch (FP) and 54nm contacted poly pitch (CPP) as well as the high density SRAM cell size of 0.0262 um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is the smallest in the reported FinFET platform. Further scaling is secured with special constructs and the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> generation single diffusion break. Full working of 256M bit SRAM and large-scale logic test chip was demonstrated with guaranteed reliability.
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C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 369 citations
Engineering, Computer Engineering, Electrical Engineering +17