C. Faulkner

Fermi-level depinning for low-barrier Schottky source/drain transistors

Daniel Connelly, C. Faulkner, P.A. Clifton et al. · Applied Physics Letters · 2006 · 158 citations

Materials Science, Electrical Engineering, Engineering +10

A New Route to Zero-Barrier Metal Source/Drain MOSFETs

Daniel Connelly, C. Faulkner, D. E. Grupp et al. · IEEE Transactions on Nanotechnology · 2004 · 127 citations

Electrical Engineering, Semiconductor Device, Engineering +12

Plasma etch technologies for the development of ultra-small feature size transistor devices

Dipu Borah, M. T. Shaw, Sozaraj Rasappa et al. · Journal of Physics D Applied Physics · 2011 · 86 citations · Full text

Engineering, Electron-beam Lithography, Nanodevices +26

Performance advantage of schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate cmos

Daniel Connelly, C. Faulkner, D. E. Grupp · IEEE Transactions on Electron Devices · 2003 · 53 citations

Engineering, Vlsi Design, Power Electronics +16

Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance

Daniel Connelly, C. Faulkner, D. E. Grupp · IEEE Electron Device Letters · 2003 · 50 citations

Low-power Electronics, Electrical Engineering, Engineering +11