Saleh Karman

A 30-GHz Digital Sub-Sampling Fractional-$N$ PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS

Luca Bertulessi, Saleh Karman, Dmytro Cherniak et al. · IEEE Journal of Solid-State Circuits · 2019 · 31 citations

Engineering, Electrical Engineering, Low-power Design +16

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping

Simone M. Dartizio, Francesco Tesolin, Mario Mercandelli et al. · IEEE Journal of Solid-State Circuits · 2021 · 29 citations

Engineering, Computer Engineering, Electrical Engineering +17

Jitter Minimization in Digital PLLs with Mid-Rise TDCs

Luca Avallone, Michael Peter Kennedy, Saleh Karman et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2019 · 22 citations

Engineering, Computer Engineering, Electrical Engineering +17

16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs<inf>rms</inf> Jitter in 65nm LP CMOS

Luigi Grimaldi, Luca Bertulessi, Saleh Karman et al. · 2019 · 20 citations

Engineering, Electrical Engineering, Analog Electronics +14

32.3 A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter

Mario Mercandelli, Alessio Santiccioli, Simone M. Dartizio et al. · 2021 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +17