Luca Avallone

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs

Luca Avallone, Mario Mercandelli, Alessio Santiccioli et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2021 · 39 citations

Electrical Engineering, Engineering, Accurate Linearized Model +14

A Fractional-<i>N</i> Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time

Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin et al. · IEEE Journal of Solid-State Circuits · 2022 · 37 citations · Full text

Adaptive Frequency Switching, Electrical Engineering, Engineering +14

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping

Simone M. Dartizio, Francesco Tesolin, Mario Mercandelli et al. · IEEE Journal of Solid-State Circuits · 2021 · 29 citations

Engineering, Analog-to-digital Converter, Radio Frequency +14

Jitter Minimization in Digital PLLs with Mid-Rise TDCs

Luca Avallone, Michael Peter Kennedy, Saleh Karman et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2019 · 22 citations

Engineering, Analog-to-digital Converter, Clock Recovery +11

A 68.6fs_rms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching

Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin et al. · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 21 citations

Electrical Engineering, Engineering, High-frequency Device +11