Francesco Tesolin

A Fractional-<i>N</i> Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time

Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin et al. · IEEE Journal of Solid-State Circuits · 2022 · 37 citations · Full text

Adaptive Frequency Switching, Electrical Engineering, Engineering +14

4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro et al. · 2023 · 35 citations

Wireless Communications, Electrical Engineering, Engineering +14

A Low-Spur and Low-Jitter Fractional- <i>N</i> Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro et al. · IEEE Journal of Solid-State Circuits · 2023 · 35 citations · Full text

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

Giacomo Castoro, Simone M. Dartizio, Francesco Tesolin et al. · 2023 · 33 citations

Pll Spectrum, Dtc Non-linearity, Dtc Control Word +11

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping

Simone M. Dartizio, Francesco Tesolin, Mario Mercandelli et al. · IEEE Journal of Solid-State Circuits · 2021 · 29 citations

Engineering, Analog-to-digital Converter, Radio Frequency +14