Giacomo Castoro

4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro et al. · 2023 · 35 citations

Wireless Communications, Electrical Engineering, Engineering +14

A Low-Spur and Low-Jitter Fractional- <i>N</i> Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro et al. · IEEE Journal of Solid-State Circuits · 2023 · 35 citations · Full text

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

Giacomo Castoro, Simone M. Dartizio, Francesco Tesolin et al. · 2023 · 33 citations

Pll Spectrum, Dtc Non-linearity, Dtc Control Word +11

10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fs_rms Integrated Jitter and −252.4dB FoM

Michele Rossoni, Simone M. Dartizio, Francesco Tesolin et al. · 2024 · 25 citations

A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC

Michele Rossoni, Simone M. Dartizio, Francesco Tesolin et al. · IEEE Journal of Solid-State Circuits · 2024 · 13 citations