MorphoSys: An Integrated Re-configurable Architecture

Abstract

In this paper, we present the MorphoSys reconfigurable architecture, which combines a configurable array of processing elements with a RISC processor core. We provide a system-level model, describing the array architecture and the inter-connection network. We give several examples of applications that can be mapped to the MorphoSys architecture. We also show that MorphoSys achieves performance improvements of more than an order of magnitude as compared to other implementations and processors.