Baring it all to software: Raw machines

TLDR

Raw processors are highly parallel architectures comprising hundreds of simple tiles with small on‑chip memory, each tile featuring configurable logic for hardware synthesis, and unlike conventional designs they eschew a traditional ISA, making the compiler’s effectiveness the main limitation. Programs are compiled directly onto the Raw hardware, with the compiler explicitly instructing each unit and scheduling most inter‑tile communication. The authors show impressive speedups on simple algorithms suited to this model, but its applicability to future workloads remains uncertain.

Abstract

The most radical of the architectures that appear in this issue are Raw processors-highly parallel architectures with hundreds of very simple processors coupled to a small portion of the on-chip memory. Each processor, or tile, also contains a small bank of configurable logic, allowing synthesis of complex operations directly in configurable hardware. Unlike the others, this architecture does not use a traditional instruction set architecture. Instead, programs are compiled directly onto the Raw hardware, with all units told explicitly what to do by the compiler. The compiler even schedules most of the intertile communication. The real limitation to this architecture is the efficacy of the compiler. The authors demonstrate impressive speedups for simple algorithms that lend themselves well to this architectural model, but whether this architecture will be effective for future workloads is an open question.