Reconfigurable Array Architecture

A Reconfigurable Array Architecture is a parallel processing architecture consisting of a grid of coarse-grained computational units interconnected via a configurable network, distinguished by its ability to dynamically reconfigure both the functional behavior of individual units and their interconnections to adapt to diverse application workloads.

386

Publications

18K

Citations

1.1K

Authors

392

Institutions

Publications per year

2017–2026

67

Authors

1.1K

  1. KC
    Ki‐Young Choi

    Seoul National University, South Korea

    11 publications · 322 citations

    11

    h-index

  2. SH
    Scott Hauck

    University of Washington, United States

    8 publications · 1.7K citations

    8

    h-index

  3. RW
    Reiner W. Hartenstein

    University of Kaiserslautern, Germany

    8 publications · 331 citations

    8

    h-index

  4. JT
    Jürgen Teich

    Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany

    6 publications · 96 citations

    6

    h-index

  5. SH
    Shi‐Jinn Horng

    National Taiwan University of Science and Technology, Taiwan

    6 publications · 112 citations

    6

    h-index

1–5 of 1.1K

Venues

  1. IEEE Transactions on Computers

    19 publications · 1.7K citations

    14

    h-index

  2. 11

    h-index

  3. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 8 publications · 256 citations

    8

    h-index

  4. IEEE Journal of Solid-State Circuits

    5 publications · 491 citations

    5

    h-index

  5. Proceedings of the International Conference on Parallel Processing

    Conference · 5 publications · 176 citations

    5

    h-index

1–5