Enhanced Reliability and Controllability in Filamentary Oxide‐Based 3D Vertical Structured Resistive Memory with Pulse Scheme Algorithm for Versatile Neuromorphic Applications

Abstract

Abstract This study explores the application of the incremental step pulse with verify algorithm (ISPVA) scheme in Pt/TiO X /TiN vertical resistive random‐access memory (VRRAM) devices to enhance both the reliability and controllability of resistive switching. ISPVA improves the linearity and symmetry of resistive switching, enabling accurate representation of up to 6‐bit states and ensuring precise transitions between low and high resistance states. Additionally, ISPVA ensures consistent current states across different layers, thereby improving electrical response uniformity and enhancing the performance of multilayer structures for high‐density applications. These improvements provide a stable memory window and guarantee the device's endurance for up to 1000 cycles. This study further demonstrates the implementation of various synaptic memory functions, including spike‐time‐dependent plasticity (STDP), spike‐number‐dependent plasticity (SNDP), spike‐amplitude‐dependent plasticity (SADP), spike‐duration‐dependent plasticity (SDDP), and spike‐rate‐dependent plasticity (SRDP). The findings also demonstrate that nociceptive and Pavlovian characteristics can be achieved for on‐receptor computing and associative learning. By integrating ISPVA and advanced fabrication techniques, VRRAM devices can effectively address challenges such as device‐to‐device variability and stochastic properties, thereby establishing a new benchmark for next‐generation computing and memory technologies.