Achieving 1-nm-Scale Equivalent Oxide Thickness Top-Gate Dielectric on Monolayer Transition Metal Dichalcogenide Transistors With CMOS-Friendly Approaches

Abstract

Monolayer two-dimensional transition metal dichalcogenides (2-D TMDs) are promising semiconductors for future nanoscale transistors owing to their atomic thinness. However, atomic layer deposition (ALD) of gate dielectrics on 2-D TMDs has been difficult, and reducing the equivalent oxide thickness (EOT) with CMOS-compatible approaches remains a key challenge. Here, we report ultrathin top-gate dielectrics on monolayer TMDs using industry-friendly approaches, achieving 1-nm-scale top-gate EOT. We first show ALD of HfO2 on both monolayer WSe2 and MoS2 with a simple Si seed, enabling EOT <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx ~0.9$ </tex-math></inline-formula> nm with subthreshold swing SS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx ~70$ </tex-math></inline-formula> mV/dec, low leakage, and negligible hysteresis on MoS2. We also demonstrate direct ALD of ultrathin alumina (AlOx) on monolayer MoS2 with good quality and uniformity using triethylaluminum (TEA) precursor, followed by ALD of HfO2. Combining our findings, we show that the threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {T}}$ </tex-math></inline-formula>) can be controlled by the interfacial dielectric layer on the 2-D transistor channel.