A Study of Low Temperature SoIC Targeting 200 nm Bond Pitch

Abstract

The increasing sophistication of generative AI models requires computing performance and energy efficiency scaling that Moore’s Law scaling of transistors alone cannot deliver. System technology co-optimization (STCO) by system integration of heterogeneous chiplets has proliferated across generative AI and high performance computing platforms through the tight integration of advanced node logic and high bandwidth memory. The increased interconnect density of memory to logic in 3DIC stacking enables higher bandwidth and compute performance at a lower energy consumption. System on integrated chips (SoIC) is a front-end 3DIC technology enabling 3D stacked chiplets with ultra-high interconnect density and high energy efficient performance (EEP). Scaling of the SoIC bond pitch from the micron scale to the deep sub-micron scale significantly increases EEP. Bonding at the deep sub-micron scale integrates the bond pads directly within the intermetallic routing layers of the back end of line (BEOL) metal layers, enabling the reduction of the total number of BEOL metal layers. Routing between chiplets can be further optimized to reduce both total wirelength as well as wirelength distribution to enable lower energy/bit and latency.In this paper we present preliminary study results of wafer on wafer SoIC bonding targeting a 200 nm bond pitch with a low temperature anneal (<280 C). We have optimized the bonding overlay through improvements to both the incoming wafer process as well as the wafer bonder. The correlation between electrical results and overlay will be discussed in detail.