2024 · 15 citations · 4 references
EngineeringComputer EngineeringComputer SystemsDigital CommunicationStorage SystemsSystem-on-chip DesignEmbedded Memory BlocksI/o ArchitectureMemory DevicesMemory Hierarchy DesignBandwidth EnhancementBandwidth ExtensionBandwidth Extension TechniquesGddr Memory SystemsHigh PerformanceHigh-speed I/o Circuit DesignMemory Bandwidth OptimizationPulse Modulation
GDDR memory has consistently maintained a leading position in delivering high performance: necessary for applications such as artificial intelligence, deep learning, and data centers. However, achieving an elevated I/O bandwidth, beyond the latest 27Gb/s GDDR6 [1], presents significant challenges in ensuring a sufficient I/O link budget. One solution is using multi-level pulse amplitude modulation (PAM) signaling. In the GDDR7 I/O specification, single-ended PAM3 signaling is used to achieve higher data rates as it can transfer data more than 58% faster, compared to non-return-to-zero (NRZ) signaling. Furthermore, PAM3 offers a 50% larger voltage sensing margin than PAM4, which was adopted for GDDR6X [2]. Therefore, PAM3 exhibits a higher potential for bandwidth extension, given that single-ended signaling is vulnerable to random noise and crosstalk.
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25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling
Timothy M. Hollis, Ronny Schneider, M. Brox et al. · 2021 · 25 citations
Daewoong Lee, Hye-Jung Kwon, Daehyun Kwon et al. · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 15 citations