A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier

Abstract

This article proposed a deep-pipelined analog-to-digital converter (ADC) that utilizes an input-split fully differential ring amplifier (ringamp, RAMP). The implemented ringamp is optimized for speed, achieving a higher nondominant pole frequency, and exhibits excellent adaptability in low-voltage, deep-nanoscale advanced CMOS processes. To minimize nonoverlap time, a nonoverlapping optimized clock generator is employed, generating two-phase and nonoverlapping clocks with near 50% duty cycles for sampling and amplification in the multiplying digital-to-analog converters (MDACs). The ADC architecture comprises a high-linearity input buffer, ten MDACs, and a flash backend ADC. To enhance linearity, a dither signal is injected in the first three stages. Fabricated in a 28-nm CMOS process, the 1-GS/s 12-bit ADC based on the ringamp achieves a spurious-free dynamic range (SFDR) of 70.34 dB and a signal-to-noise-and-distortion ratio (SNDR) of 55.71 dB at Nyquist input, while consuming only 38.9 mW from a single 1-V supply. This translates to a Walden figure of merit (FoM) of 75 fJ/conversion step and a Schreier FoM of 157.2 dB, respectively.