PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology

Abstract

This paper evaluates Power-Performance-Area (PPA) tradeoffs and integration challenges of three types of backside power connections: Through Silicon Via in the Middle Of Line (TSVM), Self-Aligned Front-to-Back via (BPR) and Backside contact (BSC) for nanosheets at N2 and A14 nodes. From TSVM to BPR to BSC, solid PPA gain s are shown for High Density Logic, at the expense of increased process complexity. While TSVM remains competitive in N27-Track high-performance technology, BSC shows maximal gain s in A145-Track high density node.