A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET

Abstract

Efficient time-interleaved (TI) analog-to-digital converters (ADCs) that operate at high sample rates with wide input bandwidths are necessary to support increasing wireline transceiver data rates. This article presents a 7-bit 38-GS/s 32-way TI ADC that utilizes an eight-way interleaver architecture based on a speed-enhanced bootstrapped switch that increases input bandwidth. ADC sample rate and efficiency is improved with pipelined-successive approximation register (SAR) unit ADCs that employ an output level shifting (OLS) settling technique in the dynamic residue amplifier to achieve settling in only 33% of the time required for a conventional current-mode logic (CML) amplifier. Using parallel comparators in the two 4-bit asynchronous pipeline stages allows for further improvements in ADC conversion speed. Fabricated in 22-nm FinFET, the proposed ADC occupies 0.107-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area. Operating at 38 GS/s, the ADC achieves 41.9 fJ/conv.-step with low input frequencies, 64.1 fJ/conv.-step at Nyquist, and has 20-GHz 3-dB input bandwidth.