A 2.4-GHz Sub-Sampling PLL With an Adaptive and No Power Contribution FLL Achieving 103.58 fs rms Jitter and −257.8 dB FOM

Abstract

A sub-sampling PLL (SSPLL) employing an adaptive frequency-locked loop (FLL) without static power consumption is proposed in this letter. A new unlock detection mechanism and a configurable PFD are realized in the adaptive FLL. With the new unlock detection mechanism, while the FLL that contains phase detector, divider, and charge pump dissipates no power during the locked steady state, it automatically starts when external interferences disturb the locked state. The optimized dead zone in the configurable PFD ensures a rapid relocking operation. Based on the proposed adaptive FLL, the 2.4 GHz SSPLL is fabricated in a 40-nm CMOS process. It achieves −128.5 dBc/Hz at 1 MHz offset frequency and the rms jitter is 103.58 fs integrated from 10 k to 10 MHz. It consumes 1.55 mW at 1 V supply and achieves −257.8 dB FOM.