5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O

Kaveh Hosseini, Edwin Kok, Sergey Shumarayev, Daniel Jeong, Allen Chan, Austin Katzin, Songtao Liu, Radek Roucka, Manan Raval, Minh Mac,

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 25 citations · 0 references

Concepts

Abstract

Heterogenous co-packaging of optical I/O with compute, memory or switch nodes will deliver significant improvements in power, bandwidth and reach in data center and high-performance computing applications. A first-ever real-ized and validated 5.12 Tbps co-packaged FPGA with optical I/O is presented. The Multi-Chip Package integrates a 14nm FPGA die with five Ayar Labs TeraPHY™ optical I/O chiplets.