2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 21 citations · 0 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysSystem-on-chip DesignAccelerator ArchitectureCoarse-grained Reconfigurable ArchitecturesField-programmable Gate Array ArchitectureHardware AccelerationReconfigurable AcceleratorsReconfigurable System ArchitectureAcceleratorsComplex ArithmeticDense Linear AlgebraEnergy-delay TradeoffEnergy-efficient Hardware AccelerationPower-efficient Accelerator DesignReconfigurable Accelerator DesignReconfigurable Architectures
Amber is a system-on-chip (SoC) with a coarse-grained reconfigurable array (CGRA) for acceleration of dense linear algebra applications such as machine learning (ML), image processing, and computer vision. It achieves a peak energy efficiency of 538.0 INT16 GOPS/W and 483.3 BFloat16 GFLOPS/W. We maximize CGRA utilization and minimize reconfigurability overhead through (1) dynamic partial reconfiguration of the CGRA that enables higher resource utilization by allowing multiple applications to run at once, (2) efficient streaming memory controllers supporting affine access patterns, and (3) low-overhead transcendental and complex arithmetic operations. Compared to a CPU, a GPU, and an FPGA, Amber achieves up to 3902x, 152x, and 88x better energy-delay product (EDP).