3D Packaging for Heterogeneous Integration

TLDR

Next‑generation high‑performance devices require higher density, bandwidth, reduced interconnects, greater energy efficiency, and smaller footprints, making chiplet architecture and advanced packaging essential for heterogeneous integration amid Moore’s Law slowdown. This paper investigates AMD’s advanced package architectures that deliver power, performance, area, and cost (PPAC) improvements while enabling heterogeneous integration. The authors detail AMD’s 3D V‑Cache architecture, which uses direct Cu‑Cu bonding to achieve these PPAC gains. Package‑level results show that the direct Cu‑Cu bonding in AMD’s 3D V‑Cache yields significant PPAC improvements.

Abstract

The next generation of competitive integrated high-performance devices demand increased device density, higher memory bandwidth, reduced global interconnects, increased energy efficiency, and a smaller footprint. Chiplet architecture is now recognized as fundamental to enabling the continued economically viable growth of power efficient computing given the slowdown in Moore's Law. Advanced packaging technologies and architectures are becoming more critical to enabling the next frontier through heterogeneous integration. In this paper, we will cover the advanced package architectures being enabled by AMD to provide power, performance, area, and cost (PPAC) improvements as well as to enable heterogeneous architectures. The direct Cu-Cu bonding technology used in AMD 3D V-Cache architecture is detailed and package level results are presented.