64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique

Abstract

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power and two-ported functionality. However, it refresh requirement also results in power consumption and memory access limitations. In this paper, we present a GCeDRAM architecture designed to overcome the refresh disadvantages using a novel technique for improving the availability of the memory. In addition, by using a read-before-write mechanism, half-select is supported. The macro avoids the need for supply boosting by employing 3T-1C bitcells, and also integrates a replica bit-line for optimal access timing to improve performance and power consumption. A 64kB GC-eDRAM macro was fabricated in a 65nm process technology, providing a 40% area reduction compared to a 6T SRAM cell, while achieving a 99.99% bit yield with a 16 ls retention time.