FPGA Implementation of Approximate Multiplier with Edge Detection Application

Abstract

Approximation is a trending area in the world of digital circuits. This work is based on the idea that many application can sanction a certain level of approximation in it’s design and when approximation is introduced into a design,it can efficiently improve the speed, area and time requirement of the device. In this work, the multiplier is modeled on an approximate calculation in the VERILOG Hardware Description Language (HDL) using Xilinix. Thus, this paper introduces an approximate multiplier with improved area, power, and timing requirements. The design is primarily aimed at a specific application, image processing. The design is compared to regular multipliers and emphasizes areas, power, and time improvements. The proposed multiplier is created by Verilog HDL, simulated by Modelsim, and synthesized by the Xilinx Vivado tool.