IEEE Transactions on Computers · 2014 · 620 citations · 15 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignMicroelectronicsData CompressionDigital Image ProcessingImage CompressionImage ProcessingLow-power Digital Circuit DesignTiming AnalysisApproximate ComputingApproximate Computing For Low PowerApproximate Computing For Power ReductionCompressorsError Rate AnalysisMultiplier DesignMultipliersPower Consumption
Inexact computing is an attractive paradigm for digital processing at nanometric scales and is particularly interesting for computer arithmetic designs. This paper analyzes and designs two new approximate 4‑2 compressors for use in a multiplier. The compressors exploit different compression features to balance imprecision—measured by error rate and normalized error distance—with circuit metrics such as transistor count, delay, and power, and four utilization schemes are proposed and analyzed for a Dadda multiplier. Extensive simulations and an image‑processing application demonstrate that the proposed compressors achieve significant reductions in power, delay, and transistor count versus an exact design, and two multiplier variants deliver excellent image multiplication performance with average normalized error distance and peak signal‑to‑noise ratios exceeding 50 dB.
Inexact (or approximate) computing is an attractive paradigm for digital processing at nanometric scales. Inexact computing is particularly interesting for computer arithmetic designs. This paper deals with the analysis and design of two new approximate 4-2 compressors for utilization in a multiplier. These designs rely on different features of compression, such that imprecision in computation (as measured by the error rate and the so-called normalized error distance) can meet with respect to circuit-based figures of merit of a design (number of transistors, delay and power consumption). Four different schemes for utilizing the proposed approximate compressors are proposed and analyzed for a Dadda multiplier. Extensive simulation results are provided and an application of the approximate multipliers to image processing is presented. The results show that the proposed designs accomplish significant reductions in power dissipation, delay and transistor count compared to an exact design; moreover, two of the proposed multiplier designs provide excellent capabilities for image multiplication with respect to average normalized error distance and peak signal-to-noise ratio (more than 50 dB for the considered image examples).
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