Publication | Closed Access
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors
37
Citations
8
References
2002
Year
EngineeringAccelerated DesignEnergy EfficiencyElectronic Design AutomationPower Optimization (Eda)Computer ArchitecturePower OptimizationDual-vt Process TechnologySocial SciencesComputer DesignDesign MigrationModeling And SimulationParallel ComputingPower-aware DesignPower ManagementTotal Power OptimizationDesign Space ExplorationPower-aware ComputingElectrical EngineeringVt AllocationDevice SizingDesignComputer EngineeringIndustrial DesignSimultaneous Dual-vt AllocationPower-efficient Computing
We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5/spl times/ larger computation runtime than iSTATS due to its iterative nature.
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