2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003 · 45 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSystem-on-chip DesignClock Distribution NetworksClock ManagementClock SynchronizationProcessor Core DesignProcessor MicroarchitectureTiming AnalysisClock ConfigurationClock DistributionClock Distribution DesignClock Network ArchitectureJitterJitter Control
The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.
2
A clock distribution network for microprocessors
P.J. Restle, T. G. McNamara, Daniel Webber et al. · IEEE Journal of Solid-State Circuits · 2001 · 302 citations
Engineering, Computer Engineering, Electrical Engineering +17