1991 · 12 citations · 1 references
EngineeringComputer EngineeringComputer ArchitectureMicroelectronicsSystem-on-chip DesignBuilt-in Self-testDesign For TestabilityMemory Hierarchy DesignMemory Subsystem DesignMemory TestParallel TechniquePhotolithographyTest Time Efficiency
This single 3.3V 64Mb DRAM uses currently-available 0.4μm CMOS photolithography (i-line). In this RAM, merged match line test (MMT) data-line architecture provides both faster access time and shorter test time, with minimum chip area penalty. Using a parallel MMT technique, which is an extension of MMT, a 64kb parallel test is executed.
1
A 1.5 V circuit technology for 64 Mb DRAMs
Y. Nakagome, Y. Kawamoto, Hiroki Tanaka et al. · 1990 · 51 citations
Engineering, Computer Engineering, Electrical Engineering +17