A 1.5 V circuit technology for 64 Mb DRAMs

Y. Nakagome, Y. Kawamoto, Hiroki Tanaka, Kazuhiro Takeuchi, E. Kume, Yoshio Watanabe, T. Kaga, Fabrício Murai, R. Izawa, Digh Hisamoto,

1990 · 51 citations · 0 references

Concepts

Abstract

A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future