2002 · 38 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSystem-on-chip DesignCmos Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignPower ManagementProcessor Core DesignVoltage ScalingDynamic Power DissipationDynamic Voltage And Frequency ScalingEnergy-efficient Digital CircuitsLow-power Cmos DesignLow-power MicroarchitectureLow-voltage Cmos DesignThreshold VoltageUltra-low-power Cmos
This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 0.9 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed, standby power and chip area.
3
200 MHz video compression macrocells using low-swing differential logic
M. Matsui, Hiroyuki Hara, K. Seta et al. · 2002 · 47 citations
Engineering, Computer Engineering, Electrical Engineering +11