Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

Abstract

In order to overcome the limitation of cell area of 4F/sup 2/ per bit in conventional NAND flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. The new structured cell achieves cell area of 4F/sup 2//N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of 2 stacked memory cells in one silicon pillar achieves cell area per bit less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2/spl mu/m design rule. The S-SGT, structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, the same as conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories as large as 16G/64G bit flash memory or beyond.