2009 · 20 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringEmbedded SystemsLow-power DesignSystem-on-chip DesignPower ManagementPower OptimizationTemperature MeasurementThermal ManagementThermal SensorsVoltage ScalingClock DistributionDynamic Frequency ScalingDynamic ScalingDynamic Temperature ControlDynamic Voltage And Frequency ScalingSupply Voltage OptimizationSystem-on-chip Power ManagementThermal Sensing
Ring‑oscillator frequency decreases linearly with temperature, enabling on‑chip temperature sensing. The authors propose an oscillation‑based thermal sensing architecture and a DF2VS algorithm to dynamically adjust supply voltage and clock frequency across SoC hot spots. An on‑chip DVS/DVFS monitor selects voltage and frequency levels based on outputs from the ring‑oscillator thermal sensors distributed throughout the SoC. Experiments on SoC benchmarks show that a 10 % voltage reduction yields ~20 % power savings, while adding frequency scaling achieves ~50 % power reduction and lowers chip temperature.
A novel oscillation-based on-chip thermal sensing architecture for dynamically adjusting supply voltage and clock frequency in System-on-Chip (SoC) is proposed. It is shown that the oscillation frequency of a ring oscillator reduces linearly as the temperature rises, and thus provides a good on-chip temperature sensing mechanism. An efficient Dynamic Frequency-to-Voltage Scaling (DF2VS) algorithm is proposed to dynamically adjust supply voltage according to the oscillation frequencies of the ring oscillators distributed in SoC so that thermal sensing can be carried at all potential hot spots. An on-chip Dynamic Voltage Scaling or Dynamic Voltage and Frequency Scaling (DVS or DVFS) monitor selects the supply voltage level and clock frequency according to the outputs of all thermal sensors. Experimental results on SoC benchmark circuits show the effectiveness of the algorithm that a 10% reduction in supply voltage alone can achieve about 20% power reduction (DVS scheme), and nearly 50% reduction in power is achievable if the clock frequency is also scaled down (DVFS scheme). The chip temperature is reduced accordingly.
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