Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) · 2002 · 13 citations · 1 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureDesign AutomationHardware Description LanguagesDelay ModelingDesign HierarchyHierarchical DesignLogic SynthesisTiming AnalysisTiming ModelingModel-based Hardware DesignNetlist Generation
The automated generation of timing models from gate-level netlists facilitates IP reuse and dramatically improves chip-level STA runtime in a hierarchical design flow. In this paper we discuss two different approaches to model generation, the design flows they lend themselves to and results from the application of these model generation solutions to large customer designs.
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Timing abstraction of intellectual property blocks
Svetha Venkatesh, Robert Palermo, Mohammad Mortazavi et al. · 2002 · 22 citations
Engineering, Computer Engineering, Electrical Engineering +17