1991 · 17 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMemoryMicroelectronicsMemory DevicesMemory Subsystem DesignElectronic ComputersFlash MemoryFlash Memory DevicesFloating-gate MemoryMemory Array ArchitectureNon-volatile Memory DesignNonvolatile Memory
An erase and program control system is used in this 60ns 16Mb flash EEPROM intended for internal and external storage in the palm-top and notebook personal computers. The stackedgate flash EEPROM demonstrates that an electrically-erasable nonvolatile memory can be constructed in almost the same chip area as UV-erasable EPROM.1• 2 However, there are several problems to be solved in high-density flash EEPROM beyond 16Mb. The problems related to the erasure operation are: 1) overerasure of the 16Mb memory array, 2) large Vpp current caused by the band-to-band tunneling at the source region overlapping the floating gate of memory cells, and 3) long erasure time resulting from programming-before-erasure.
2
A 90-ns one-million erase/program cycle 1-Mbit flash memory
V. Kynett, M.L. Fandrich, J. Anderson et al. · IEEE Journal of Solid-State Circuits · 1989 · 53 citations
A flash-erase EEPROM cell with an asymmetric source and drain structure
Haruki Kume, H. Yamamoto, T. Adachi et al. · 1987 · 37 citations
Engineering, Computer Engineering, Electrical Engineering +14