8Gb 3D DDR3 DRAM using through-silicon-via technology

Abstract

DRAMs in modules are preferably arranged in multiple ranks to increase system band-width. However, this limits the input/output (I/O) speed since increased channel loading causes degradation in signal integrity. To overcome the I/O speed limit, several buffered module solutions have been proposed, where data pins are buffered by additional chips. However, this increases power consumption and latency significantly. We present a 3D DRAM with TSVs that overcomes the limits of conventional module approaches. Important architectural aspects, and key 3D technologies such as inter-rank seamless read scheme, TSV check and repair scheme, and a power-noise reduction method are presented.