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Dynamic-sleep transistor and body bias for active leakage power control of microprocessors
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2003
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Hardware SecurityLow-power ElectronicsPower-aware ComputingElectrical EngineeringEngineeringVlsi DesignActive LeakagePower Optimization (Eda)Multi-channel Memory ArchitectureComputer EngineeringComputer ArchitectureBody BiasDynamic-sleep TransistorSleep TransistorsPower ManagementMicroelectronicsPower-aware DesignPower Electronic Devices
Sleep transistors and body bias are used to control active leakage for a 32b integer execution core implemented in a 100nm dual V, CMOS technology. A PMOS sleep transistor degrades performance by 4% but offers 20/spl times/ leakage reduction which is further improved with body bias. Time constants for leakage convergence range from 30ns to 300ns allowing 9-44% power savings for idle periods greater than 100 clock cycles.