Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

Abstract

An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this article. Increased bitline (BL) resistance in sub-10 nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an increased leakage current of half-selected bitcells on BL and BL capacitance operated in high frequency. In a realistic write operation, BL parasitics also cause 30% SRAM yield loss in interconnect resistance-dominated technology nodes. Thus, this proposed method analyzes the time-dependent impacts of BL parasitic resistors, capacitors, and pass-gate (PG) transistors on write margin considering the negative BL (NBL) assist technique.