Advanced Scaling of Enhancement Mode High-K Gallium Nitride-on-300mm-Si(111) Transistor and 3D Layer Transfer GaN-Silicon Finfet CMOS Integration

Abstract

We demonstrate scaling of an enhancement-mode (E-mode) high-k GaN-on-300mm Si(111) NMOS transistor achieving best-in-class performance and figure-of-merits for integrated power electronics and RF mm-wave. Here, we demonstrate many firsts and industry records for GaN-on-Si, including record f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> /f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> of 300/400GHz and transconductance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{G}_{\mathrm{M}} &gt; 2100 \mu\mathrm{S}/\mu \mathrm{m}$</tex> with industry thinnest <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\text{OXE}}= 14.8 \mathrm{\AA}$</tex> ; record high <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{DS}}= 65\mathrm{V}$</tex> for a 30nm channel length GaN transistor with excellent <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{R}_{\text{ON}}= 495\Omega-\mu \mathrm{m}$</tex> ; first truly e-mode GaN achieving full ON-current with record low-gate-drive, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{Gon}}= 1.8\mathrm{V}, \mathrm{I}_{\text{OFF}}= 25\text{pA}/\mu \mathrm{m}$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\mathrm{D}}=30\mathrm{V}\ (\mathrm{V}_{\mathrm{G}}=0\mathrm{V})$</tex> ; high-Q MIM and inductor enabled by GaN industry's first 4-metal layer Cu backend interconnect process on 300mm silicon; outstanding RF performance: 24dBm RF output power <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\mathrm{D}}= 10\mathrm{V}$</tex> and high power density 2.7W/mm at 28GHz; 17.6dBm (0.72W/mm) with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{PAE}=20.1\%$</tex> at 76GHz, and 0.4W/mm with 10.5% PAE and 4.3dB gain at 90GHz. All these are accomplished on a highly uniform 300mm GaN process capable of tight threshold voltage variation <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(1\sigma)$</tex> of 38mV across the wafer, setting an industry milestone for GaN-on-Si. Finally, inspired by Moore's law, as we look ahead to the future of GaN transistor technology, we show that it is possible to integrate GaN NMOS finfet <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{W}_{\text{fin}}=25\text{nm})$</tex> , the narrowest GaN fin ever been demonstrated, and Si PMOS finfet <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{W}_{\text{fin}}=35\text{nm})$</tex> technologies with matched V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> and drive ratio, by fabricating and demonstrating a low-leakage 3D-stacked GaN-Si CMOS inverter using the 3D layer transfer technology [1], [2].