Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) · 2002 · 379 citations · 0 references
Hardware SecuritySystem On ChipEngineeringOn-chip Interconnection NetworksComputer EngineeringComputer ArchitectureRoutingRoute PacketsSimple NetworkStructured NetworkComputer ScienceInterconnection NetworkNetwork On ChipParallel ComputingInterconnection Network ArchitectureMicroelectronicsHardware Architecture
On‑chip interconnection networks replace ad‑hoc global wiring, providing modular design and well‑controlled electrical parameters that eliminate timing iterations and enable high‑performance, low‑latency, high‑bandwidth operation. The paper introduces on‑chip networks, outlines a simple network design, and discusses architectural and design challenges. System modules such as processors, memories, and peripherals communicate by sending packets over the network. The on‑chip network adds modest area overhead, estimated at 6.6%.
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.