Tightly Stacked 3D Diamond-Shaped Ge Nanowire Gate-All-Around FETs With Superior nFET and pFET Performance

Abstract

We propose that the use of tightly stacked three-dimensional (3D) diamond-shaped Ge nanowire (NW) gate-all-around field-effect transistor (Ge-NW GAAFET) is a feasible approach to continuous scaling. The proposed devices with the Al₂O₃ dielectric exhibit high I_SAT of 1200 <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\mu } \text{A}/\boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> (pFET) and 1100 <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\mu } \text{A}/\boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> (nFET), high I_ON/I_OFF ratio of approximately <inline-formula> <tex-math notation="LaTeX">${1} \times {10}^{{5}}$ </tex-math></inline-formula>, and steep subthreshold swing (SS) close to 70mV/dec. Superior gate control of the Ge-NW GAAFET was confirmed by the 3D TCAD simulation for the sub-3nm node applications. The formation of the tightly stacked Ge NWs is fully compatible with the complementary metal oxide semiconductor (CMOS) technology platform using only alternating isotropic and anisotropic dry etching, thus showing promising potential for extending CMOS scaling in the vertical direction.