Valid test pattern identification for VLSI adaptive test

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

Aibin Yan, Zhengfeng Huang, Maoxiang Yi et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2017 · 116 citations

Engineering, Computer Engineering, Electrical Engineering +14

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Aibin Yan, Chaoping Lai, Yinlei Zhang et al. · IEEE Transactions on Emerging Topics in Computing · 2018 · 115 citations

Engineering, Computer Engineering, Electrical Engineering +16

Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices

Cheng Zhuo, Shaoheng Luo, Houle Gan et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2019 · 83 citations

Engineering, Computer Engineering, Electrical Engineering +17

Optimal production test times through adaptive test programming

S. Benner, O. Boroffice · 2002 · 52 citations

Engineering, Industrial Engineering, Systems Engineering +13

Adaptive Test With Test Escape Estimation for Mixed-Signal ICs

Haralampos‐G. Stratigopoulos, Christian Streitwieser · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2017 · 29 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +14