CoW Package Solution for Improving Thermal Characteristic of TSV-SiP for AI-Inference

Abstract

Logic device for AI-inference needs high band width and low latency characteristics to increase the response speed. In order to overcome the size limitation of a single logic chip and secure these characteristics, it is inevitable to separate the SRAM function to increase the memory capacity and apply a 3D package structure that directly stacks with logic. The structure of stacking logic and memory can be implemented in four cases; face to face and back to face (B2F), Logic on SRAM and SRAM on Logic. Among them, thermal characteristics in SRAM on Logic with B2F are not stronger than other structures because in a server environment where most of the heat is forcibly discharged through the cooler installed on the top of package, a lot of heat generated from the logic front side does not go directly to the cooler through Si alone, but passes through the micro-bump bonding layer and the entire SRAM chip. In this study, it was presented that a detailed method for reducing the thermal resistance of the micro-bump junction in order to improve the thermal characteristics in the SRAM on Logic stack package structure. Test vehicle consisted of top chip (93mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and bottom chip (103mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) with micro-bump connections of under 40 μm in pitch and under 20 μm in diameter. The main influence factors were analyzed in terms of the joint structure, material, and layout design, and thermal resistance was measured and compared after achieving actual package to confirm exactly the effect of each major factor on reducing package thermal resistance.